In recent years, the rate of CPU performance improvement has slowed, and research of computing apparatuses capable of performing high speed calculations using a Field Programmable Gate Array (FPGA) as well as a CPU, prompting increases. Herein, an FPGA is one example of a PLD.
As an usage method of the FPGA, it is common to load FPGA configuration data in the FPGA at the time of device power-on, and use it as dedicated hardware. In this method, as FPGA configuration data is loaded only at the time of device power-on, when it is desirable to share the FPGA between multiple applications, it is necessary to load the FPGA configuration data corresponding to the functions of all the applications that will be used. In a single application, however, only a portion of the application's functionality can be utilized, and there is no guarantee that all the applications will be used, such that the FPGA cannot be used efficiently.
PTL 1 discloses a technique in which “an FPGA board (programmable logic circuit) is provided on the bus line of a CPU, circuit data to be written to the FPGA board together with the application program is loaded from an external storage apparatus such as a floppy disk apparatus, and the circuit data is written to the FPGA board such that the FPGA board can be used as a dedicated logic circuit in the application.”